ASIC EDA Infrastructure Engineer Intern

Meta

Sunnyvale, CAOn-siteInternship
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Pay
$6.7K to $12K
a month
Location
Sunnyvale, CA
Work style
On-site
Job type
Internship
Posted
Nov 4
1 day ago
Career path

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About the company

Meta

Software Development · 10,001+ employees

Meta's mission is to build the future of human connection and the technology that makes it possible.

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What you'll do

  • The intern will contribute to the development and testing of ASIC design implementation flows and automation tools.
  • They will also collaborate with infrastructure teams to improve compute grid efficiency and support design cycle productivity.

What you need

  • Candidates must be currently enrolled in a B.S. degree program in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
  • Proficiency in RTL design, scripting languages like Python, and exposure to ASIC design fundamentals are required.
  • Education: a bachelor's degree

Key skills

ASIC designEDA flowsAutomationSystemVerilogVerilogPythonTclShell scriptingRTL designGitMercurialLinuxContinuous integrationCompute infrastructureData management

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Perks

  • Mentorship
  • Onboarding support

See full description on company page, apply now

Read the full posting here
Meta is hiring ASIC EDA Infrastructure Engineer Interns within our Infrastructure ASIC organization. Our team builds the EDA flows, automation, and infrastructure behind efficient System on Chip (SoC) and IP designs for data center applications. As an intern, you'll work alongside experienced engineers on a scoped project that contributes directly to how our ASIC design teams build silicon — with mentorship, onboarding support, and regular feedback throughout your internship. This is a 12 week internship Responsibilities Contribute to the development and testing of front-end or physical design implementation flows Help build or improve internal automation tools that increase productivity across ASIC design cycles — for example, RTL generation, memory selection automation, register generation, or filelist generation Write and maintain scripts that support day-to-day design flow tasks Help document EDA flows, tool behavior, and evaluation findings for the team Partner with internal infrastructure teams on compute grid, storage, and job scheduling efficiency Support efforts to adapt Meta infrastructure to ASIC design needs, including source control, continuous integration, data management, and reporting Present your project results and recommendations to the team at the end of the internship Minimum Qualifications Currently enrolled in a B.S. degree program in Computer Engineering, Computer Science, Electrical Engineering, or a related field Coursework or project exposure to digital design or ASIC design fundamentals Exposure to RTL design using SystemVerilog, Verilog, or another HDL Programming or scripting experience in Python, exposure to Tcl or shell scripting Interest in developer tooling, automation, build systems, or compute infrastructure Ability to communicate technical work clearly and collaborate across teams Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment Intent to return to full-time degree program after completion of the internship Preferred Qualifications Hands-on exposure to industry EDA tools through coursework, a lab/research project, a tapeout or design competition, or a prior internship Experience building automation, scripts, or developer tooling in a team or open-source setting Familiarity with version control (Git/Mercurial) and continuous integration concepts Exposure to Linux environments, job scheduling, or distributed compute Demonstrated focus on user experience and customer-oriented solutions $6,660/month to $12,014/month + benefits

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