CPU Design Verification Engineer - Intern
RosaicLabs
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- Pay
- $30 to $55
- an hour
- Location
- Santa Clara, CA
- +1 more location
- Work style
- On-site
- Job type
- Internship
- Posted
- Oct 5
- 30 days ago
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Career path
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What you'll do
- You will work with a mentor to develop verification plans and debug SystemVerilog/UVM testbenches for CPU cores and cache hierarchies.
- Additionally, you will build tests, scoreboards, and reference models while triaging failures with RTL designers.
What you need
- Candidates must be working toward a BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Proficiency in digital design, verification methodologies, and scripting languages like Python, Perl, or Tcl is required.
- Education: a bachelor's degree or a postgraduate degree
Key skills
SystemVerilogUVMCPU DesignCache HierarchyFunctional CoverageCode CoverageRTL DesignDigital LogicMicroarchitecturePythonPerlTclC++ASIC Design FlowVLSICache Coherency
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Read the full posting here
Join our hardware team as an intern or co-op verifying the CPU core and cache hierarchy, with hands-on ownership of verification environments from test plan through coverage closure and bring-up.
Get hands-on exposure to chip design and verification — perfect for EE/CompE students curious about how it all comes together.
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What you'll do
Work with your mentor to develop verification plans for the CPU core and cache hierarchy
Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block
Build tests, scoreboards, and reference models, and close functional and code coverage
Triage and root-cause failures with RTL designers, with mentorship from senior engineers
Participate in design and verification reviews and document your verification environment and results
Requirements
Working toward BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
Recently completed coursework in digital design and verification, covering at least one of: computer microarchitecture; digital logic and RTL design; constrained-random and coverage-driven verification
Familiarity with verifying processor designs, such as: a modern ISA; out-of-order execution and memory ordering; cache coherency and virtual memory
Hands-on SystemVerilog experience, including: testbench development (UVM preferred); assertions and functional coverage
Understanding of the end-to-end ASIC design flow and general VLSI concepts
Scripting experience (Python, Perl, or Tcl) for regression automation; C/C++ a plus
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$30 - $55 an hour
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