Entry Level DFT Design Engineer

NXP Semiconductors

Austin, United StatesOn-siteFull time
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Location
Austin, United States
Work style
On-site
Job type
Full time
Posted
Oct 19
3 days ago
Career path

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About the company

NXP Semiconductors

Semiconductors · 10,001+ employees

NXP Semiconductors on LinkedIn

What you'll do

  • Participate in global Design teams bringing new microprocessor based SoC designs through initial test requirements
  • Generate and support DFT structural test pattern debug and full scale production
  • Specify and create test patterns
  • Perform pre-silicon verification and pattern conversions to ATE
  • Support post-silicon pattern debug
  • Specify, implement, and validate built-in test features
  • Deliver all DFT test patterns for the product
  • Interface with Test Engineering, Product Engineering, and Fab for the Design team

What you need

  • Recent graduate (0-2yrs) with Bachelors or Masters in Engineering: EE, Computer Engineering, CS, EET, or equivalent
  • Python, Verilog, Perl, Tcl, and Unix
  • Experience with multiple aspects of structural test design requirements, ATPG, test coverage, and fault universe
  • Knowledge/experience with JTAG, BSDL, Memory and Logic BIST, and DFT Logic
  • Knowledge/experience with ATPG / DFT tools: FastScan; LBIST, MBIST, DFTCompiler, etc.
  • Semiconductor Testing
  • Excellent oral and written communication skills; able to work with minimal direction and meet schedules
  • ATE VLSI Tester programming and usage (J973, Tiger/Catalyst, UltraFex, or Verigy 93000) a plus (preferred)

Key skills

PythonVerilogPerlTclUnixStructural Test designATPGTest CoverageFault UniverseJTAGBSDLMemory and Logic BISTDFT LogicSemiconductor Testing

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Read the full posting here
In this role, you will: - Participate in global Design teams bringing new microprocessor based SoC designs through initial test requirements to generating and supporting DFT structural test pattern debug and into full scale production. - Team functions include test pattern specification and creation, pre-silicon verification, pattern conversions to ATE, and post-silicon pattern debug. - Team is a part of the design organization and supports the Test Engineering team with the patterns for manufacturing test, qualification, yield enhancement, and product performance analysis. - Team serves as focal point in interfacing with Test Engineering, Product Engineering, and Fab for the Design team. - Team specifies built-in test features for the designs, implements, and validates the design. Team is responsible for delivery of all DFT test patterns for the product. Qualifications: Recent graduate (0-2yrs) with Bachelors or Masters in Engineering: EE, Computer Engineering, CS, EET, or equivalent Python, Verilog, Perl, Tcl, and Unix. Experience with multiple aspects of the following: Structural Test design requirements ATPG, Test Coverage, Fault Universe JTAG, BSDL Memory and Logic BIST DFT Logic Knowledge/experience with ATPG / DFT tools: FastScan; LBIST, MBIST , DFTCompiler, etc. Semiconductor Testing ATE VLSI Tester programming and usage (J973, Tiger/Catalyst, UltraFex, or Verigy 93000, ) a plus Knowledge/experience with functional pattern test Must possess excellent oral and written communication skills and be to partner with team members from other departments, disciplines, and cultures to achieve common goals in a high performance culture. Must have proven track record of being able to work with minimal direction and still meet schedules Must be able to multi-task and prioritize tasks to meet customer needs Anticipated hire date: Q1 2027 More information about NXP in the United States... NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. #LI-e41b

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