FPGA Intern (Summer 2027)

AstranisAstranisSan Francisco, California, United States
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Posted

9/23/2026

Employment

Intern

Range

$29 - $29/hr

Work style

On-site

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AI summary

Core responsibilities

The intern will focus on RTL development for FPGA-targeted applications and interface FPGAs with various peripherals including high-speed data converters and MCUs. They will also collaborate with electrical and software engineers to write code for interfacing and testing RTL in hardware.

Requirements overview

Candidates must be currently pursuing a B.S. or M.S. in electrical engineering, computer science, computer engineering, or an equivalent field. Applicants are required to be U.S. citizens or Green Card holders and must possess proficiency in Verilog/SystemVerilog for synthesis.

Key skills

FPGARTL DevelopmentVerilogSystemVerilogHardware DebuggingHigh Speed Data ConvertersVivado IDETCLDigital Communication TheoryJESD204BDSPRadio DesignSynthesisEmbedded SystemsCircuit Level Debugging

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Education requirements

bachelor degreepostgraduate degree

About Astranis

Industry

Space Research and Technology

Employees

562

Type

Privately Held

Size

501-1,000 employees

Astranis builds low-cost satellites for high orbits. Our first product, MicroGEO, offers the world’s lowest-cost satellite broadband. Operating in geostationary orbit, each MicroGEO satellite can provide dedicated satellites to small and medium-sized countries, Fortune 1000 companies, and other commercial customers. Astranis has built a $1 billion backlog for 12+ MicroGEO satellites launching over the next two years. Astranis also offers services across orbits and use cases. With contracts in place with Space Force, NASA, and other government partners, Astranis is working across MEO and GEO to support government science, PNT, and communications missions. Astranis has raised $750 million from top global investors and employs a team of over 400 engineers and builders, headquartered at Historic Pier 70 in San Francisco, California.

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Job categories

TechnologyEngineeringScience & Research

Description

Astranis builds advanced satellites for high orbits, expanding humanity’s reach into the solar system. Today, Astranis satellites provide dedicated, secure networks to highly-sophisticated customers across the globe— large enterprises, sovereign governments, and the US military. With five satellites on orbit and many more set to launch soon, the company is servicing a backlog of more than $1 billion of commercial contracts. Astranis is the preferred satellite communications partner for buyers with stringent requirements for uptime, data security, network visibility, and customization. Astranis has raised over $750 million from some of the world’s best investors, from Andreessen Horowitz to Blackrock and Fidelity, and employs a team of 450 engineers and entrepreneurs. Astranis designs, builds, and operates its satellites out of its 153,000 sq. ft. headquarters in Northern California, USA. FPGA Intern (Summer 2027) Internships at Astranis typically last for twelve weeks, and are hourly roles designed for students who are currently enrolled at a four-year university. As an Intern, you will have an amazing opportunity to work on hard problems — we pride ourselves on giving everyone at Astranis a chance to do meaningful work on challenging projects, no matter their seniority. Many past interns have designed and tested hardware/software that is heading to space on our first satellite, and many of them are now full-time employees at Astranis. If you have already graduated from a four-year university, please apply to be an Associate Engineer. Role: RTL Development for FPGA targeted applications Work with multiple FPGAs and toolchains Interface FPGAs with a variety of peripherals including high speed data converters, memories, MCUs Write software to interface and test RTL in hardware Collaborate closely with electrical and software engineers Requirements: US Citizenship or Green Card (This is a legal requirement; no exceptions) Currently pursuing a B.S. or M.S. in electrical engineering, computer science, computer engineering, or equivalent A passion for hardware development, including working in a fast-paced environment and hands-on design and development Experience in designing, implementing, and testing high throughput systems implemented on FPGAs Proficiency with Verilog/SystemVerilog for synthesis Don't meet them all? Not a problem. Please apply even if you do not meet all these criteria. Bonus: Experience with UVM and advanced SystemVerilog verification Experience with Xilinx FPGAs Experience with Vivado IDE, TCL Familiarity with system level estimates and implications of power, thermal, and real estate Experience with high speed data converters (ADCs, DACs, JESD204B) Experience with circuit level debugging Experience with digital communication theory and implementation, such as LDPC implementations Experience with space-based systems Experience with modern communication systems (RF, IF/IQ, time/freq domains, modulation) Experience in at least 1 domain beyond logic design. This could be DSP/radio design, software, hi-rel design (e.g. fault analysis & recover), etc. The base pay for this position is $29.00 per hour. Base Hourly Pay $29—$29 USD U.S. Citizenship, Lawful Permanent Residency, or Refugee/Asylee Status Required (To comply with U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the United States, or other protected individual as defined by 8 U.S.C. 1324b(a)(3)) Our mission and products are built for everyone, regardless of gender, race, creed, or background. We believe in a diverse and inclusive workplace, and we invite all people to join our team and bring their unique perspectives to make us stronger. SMS Terms of Service 1. When you opt in to receive SMS messages from Astranis Space Technologies Corp., we may send you messages related to your job application, including updates, interview coordination, and other recruiting communications. 2. You can cancel the SMS service at any time by replying with any of the following industry standard keywords: a. STOP b. STOPALL c. OPTOUT d. CANCEL e. END f. QUIT g. UNSUBSCRIBE h. REVOKE 3. After you opt out, we may send one final text message confirming that you have been unsubscribed. No further recruiting SMS messages will be sent unless you opt in again. 4. To opt back in, reply with any of the following industry standard keywords: a. START b. UNSTOP c. YES 5. For help, reply HELP or contact us at EMAIL or PHONE NUMBER. 6. Carriers are not liable for delayed or undelivered messages. 7. Message and data rates may apply. Message frequency may vary. Contact your wireless provider for details. 8. For more information on how we handle your data, please review our Privacy Policy at: https://www.astranis.com/legal/privacy.

Requirements

  • FPGA
  • RTL Development
  • Verilog
  • SystemVerilog
  • Hardware Debugging
  • High Speed Data Converters
  • Vivado IDE
  • TCL
  • Digital Communication Theory
  • JESD204B
  • DSP
  • Radio Design
  • Synthesis
  • Embedded Systems
  • Circuit Level Debugging

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