Mixed Signal Circuit Design Coop
Nokia
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- Location
- San Jose, CA
- Work style
- On-site
- Job type
- Full time, Internship
- Posted
- Oct 6
- 11 days ago
Career path
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About the company
Nokia
Telecommunications · 10,001+ employees
What you'll do
- Design, implement, and simulate high-speed analog circuits, including ADCs and DACs.
- Create layout floor plans to optimize performance and explore trade-offs among circuit topologies.
What you need
- <span data-teams="true">Familiarity with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.</span>
- <span data-teams="true">Familiarity with analog / mixed signal IPs or chips in deep submicron CMOS technologies.</span>
- <span data-teams="true">Good understanding of device physics and the impacts of layout effects;</span>
- <span data-teams="true">Familiarity with behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS</span><br>
- Education: a postgraduate degree
Key skills
Cadence VirtuosoSpectreIncisiveCalibreEMXTotem EM/IRVerilog-AVerilog-AMSdevice physicsdeep submicron CMOS technologies
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Read the full posting here
Number of Position(s): 2
Duration: 4+ months
Dates: January 2027 - May 2027
Location: Onsite in San Jose, CA
Educational Requirements
Currently a candidate for a master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field with an accredited school in the US.
Familiarity with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.
Familiarity with analog / mixed signal IPs or chips in deep submicron CMOS technologies.
Good understanding of device physics and the impacts of layout effects;
Familiarity with behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS
Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs
Create the layout floor plans to optimize the overall performance
Exploring the trade-offs of the different circuit topologies