RF IC Design Intern
MACOM
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- Location
- Lowell, MA
- Job type
- Full time, Internship
- Posted
- Oct 13
- 6 days ago
Career path
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About the company
MACOM
Semiconductors · 1,001 to 5,000 employees
What you'll do
- Design and analyze an LNA through the RFIC design cycle, including circuit simulation, matching network optimization, layout, EM modeling, parasitic extraction, and post-layout verification.
- Document and present findings and collaborate with RFIC, EM modeling, packaging, and validation engineers.
What you need
- Preferred qualifications include experience with Cadence Virtuoso and/or Keysight ADS, familiarity with EM simulation tools, understanding of passive component modeling and transmission line theory, and exposure to RFIC design methodologies.
Key skills
Cadence VirtuosoKeysight ADSKeysight MomentumAnsys HFSSRF measurementsPythonMATLABTransmission line theoryPassive component modelingRFIC design methodologiesCMOSSOIGaAs
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Read the full posting here
RFIC Design Engineering Intern
Position Summary
We are seeking a highly motivated RFIC Design Engineering
Intern to join our RF product development team. The intern will contribute to
the design and development of a Low Noise Amplifier (LNA) in SOI or GaAs technology,
working closely with experienced RFIC designers from initial architecture
definition through schematic design, simulation, and physical layout
preparation for tapeout.
This position offers hands-on experience with
industry-standard EDA tools, advanced RF circuit design techniques, and the
complete integrated circuit development flow.
Updated Key Responsibilities
Design
and analyze RF integrated circuits, with primary focus on Low Noise
Amplifier (LNA) development.
Participate
in the complete RFIC design cycle from concept and specification
definition through tapeout-ready layout.
Perform
circuit simulations including:
S-parameter
analysis
Noise
figure optimization
Linearity
analysis (IP3, P1dB)
Stability
verification
Corner
and Monte Carlo analysis
Develop
and optimize matching networks for performance targets including gain,
noise figure, power consumption, and linearity.
Create
and review RFIC layouts following process design rules and RF layout best
practices.
Perform
electromagnetic (EM) modeling and simulation of passive structures,
including inductors, transmission lines, transformers, baluns, and
matching networks using tools such as Keysight Momentum, FEM-based
solvers, and/or Ansys HFSS.
Correlate
EM simulation results with circuit simulations and incorporate
EM-extracted models into the RFIC design flow.
Perform
layout parasitic extraction and post-layout verification.
Document
design methodology, simulation results, and recommendations.
Present
technical findings and design reviews to engineering team members.
Collaborate
with RFIC, electromagnetic modeling, packaging, and validation engineers
throughout the development process.
Preferred Qualifications
Experience
with Cadence Virtuoso and/or Keysight ADS.
Familiarity
with EM simulation tools such as Keysight Momentum, FEM simulators, or
Ansys HFSS.
Understanding
of passive component modeling, transmission line theory, and
electromagnetic effects in integrated circuits.
Exposure
to RFIC design methodologies.
Familiarity
with CMOS or SOI or GaAs technologies.
Knowledge
of RF measurements and laboratory instrumentation such as VNAs, spectrum
analyzers, and signal generators.
Programming
experience in Python, MATLAB, or similar tools for data analysis and
automation.