Etched•San Jose, California, United StatesInvite-only right now: save jobs, track applications, build tailored resumes
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9/18/2026
Employment
Intern
Range
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Work style
On-site
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Core responsibilities
You will design microarchitecture and implement logic in Verilog while contributing to RTL block development. You will participate in the full design cycle, ranging from microarchitecture discussions to synthesis and timing feedback.
Requirements overview
Candidates should be pursuing a degree in electrical engineering, computer engineering, or a related field. Familiarity with high-speed digital logic, ASIC/SoC design concepts, and scripting languages like Python is required.
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Industry
Computer Hardware Manufacturing
Employees
544
Type
Privately Held
Size
51-200 employees
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