Timing Engineer

Job Details: Job Description: About Altera At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry. About the Role Altera is seeking a Timing Engineer to join our Physical Design organization. In this role, you will support timing analysis and closure activities for FPGA designs, working closely with experienced Timing, Physical Design, RTL Design, and Architecture engineers. You will gain hands-on experience with static timing analysis (STA), timing constraints, timing reports, timing optimization, and timing closure methodologies. The ideal candidate has a strong foundation in digital design and timing concepts and is interested in developing expertise in semiconductor timing analysis and advanced FPGA design methodologies. Key Responsibilities Support static timing analysis (STA) for block-level and subsystem-level designs. Analyze timing reports to identify setup, hold, and other timing violations and work with senior engineers to determine root causes. Support the development, review, and validation of timing constraints for FPGA designs. Analyze timing results across multiple operating conditions, process corners, and design modes. Assist with timing closure activities by identifying critical paths and providing data-driven recommendations for optimization. Support timing optimization and engineering change order (ECO) activities under the guidance of experienced engineers. Develop and maintain Python, Tcl, Perl, or similar scripts to automate timing analysis and improve engineering workflows. Assist with running and analyzing large-scale timing data and generating reports for engineering teams. Support timing budget analysis and help identify timing challenges at block and interface boundaries. Work with Physical Design and RTL engineers to investigate timing issues and evaluate potential solutions. Participate in timing methodology and flow improvements to increase efficiency, accuracy, and design quality. Document timing analysis, results, and technical findings to support design reviews and future development. Develop familiarity with industry-standard timing analysis tools, methodologies, and semiconductor design flows. Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $100,000 - $110,000 USD We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations. #LI-MD1 Qualifications: Minimum Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. 1+ year of relevant experience in timing analysis, digital design, semiconductor engineering, VLSI, ASIC, FPGA, or a related technical field. 1+ year of experience or equivalent hands-on project experience with digital logic, digital circuits, computer architecture, or integrated circuit design. 1+ year of experience or coursework involving timing analysis, simulation, design verification, or related engineering analysis. 1+ year of experience or coursework using Linux/Unix environments and technical scripting with Python, Tcl, Perl, or similar languages. Foundational understanding of digital timing concepts, setup and hold timing, clocking, and semiconductor design methodologies. Preferred Qualifications Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Experience with static timing analysis (STA), timing constraints, timing reports, or timing closure. Familiarity with concepts such as setup and hold analysis, clock skew, clock uncertainty, critical paths, timing slack, and timing exceptions. Experience with Python, Tcl, Perl, or similar scripting languages for engineering automation and data analysis. Familiarity with multi-corner/multi-mode (MCMM) timing analysis and process, voltage, and temperature (PVT) variations. Experience with FPGA, ASIC, SoC, or semiconductor design projects through professional experience, academic research, or hands-on projects. Familiarity with physical design concepts including synthesis, placement, routing, clock distribution, and design optimization. Experience working in Linux/Unix environments and with software development or version-control tools. Strong analytical and problem-solving skills with the ability to collaborate effectively across engineering teams. Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.